An effective scheme for reducing the branch penalty in a superscalar pipeline.

Branch instructions tend to generate disruption to the regular flow of instructions through the pipeline of processors, impairing the performance accordingly. To alleviate such performance damage and loss, various schemes which consider branch problems mainly in the scalar-based processors (i.e., processors with only a single pipeline) have been derived. To reduce the branch penalty in a superscalar pipeline where branch problems appear to be even more serious, an improving scheme which can properly schedule possible branch targets in available pipelines through certain necessary undoing arrangements is proposed in this paper. Application of previous schemes to the superscalar pipelines is also attempted and provided. Performance evaluation shows that in directing branch instructions and enhancing system performance for a superscalar pipeline, our scheme depicts more favourable and satisfactory results than the other schemes.