Realization of Multi-Operand Modular Adders in the FPGA technology

The paper presents the design and realization of the Multi-Operand Modular Adder (MOMA) structures in the Xilinx FPGA environment with the use of the Virtex 6 technology. The design is based on the LUTs(26x 1) that simulate small RAMs which serve as the main component for the look-up realization of addition and modulo generation. In this paper the MOMAs for modular addition of five-bit operands are shown. In the paper first the general structures of the MOMAs are considered and next two approaches to the multi-operand modulo addition are examined. Both approaches make use of the four-operand MOMAs. In the first approach, the four-operand MOMA is based on the two-operand modular adders, whereas in the second approach initially the four operand binary addition is performed, in the next stage followed by the modulo reduction. The implementation of both MOMA types is shown and analyzed with respect to hardware amount and pipelining frequency.

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