1.25GS/S 12bit and 2.27mW digital to analog converter (DAC) with 70.22 SNDR based on new hybrid R-C procedure in 180nm CMOS

This paper presents a novel fully differential high-speed and high-resolution Digital to Analog Converter (DAC) based on new reliable hybrid R-C technique. In the proposed idea the four LSB bits and eight MSB bits are implemented as a resistor string and new merged capacitor technique respectively. Applying the suggested method the SNDR and Effective Number of Bits (ENOB) of the proposed DAC achieve 70.22dB and 11.41 bit at the 1.25GS/s sampling rate correspondingly. In the proposed method the total capacitors of the 8 MSB bits are reduced up to 78% compared to the conventional one noticeably. As a result, the power consumption and speed of the suggested DAC are decreased and increased respectively. Moreover, the total power consumption of the proposed DAC is 2.27mW with the power supply of 1.8 volts as well. Meanwhile, for the correctness of the proposed 12bit DAC, 200 iterations in transient Monte-Carlo analysis (parasitic capacitance included ([symbol] mismatch = 1.2%)), and the SNDR simulation results versus different input frequency at fS=1.25GS/s sampling rate are applied too. The maximum Integral Nonlinearity (INL) and the maximum Differential Nonlinearity (DNL) are -0.47/+0.35LSB and -0.42/+0.29 LSB respectively. The proposed DAC structure is simulated in all process corners and performed using the HSPICE BSIM3 model of a 0.18μm CMOS technology.

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Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2018).