FPGA implementation of reverse residue conversion based on the new Chinese Remainder Theorem II- Part I

This work describes a derivation and an implementation of the algorithm of conversion from the Residue Number System (RNS) to the binary system based on the new form of the Chinese Remainder Theorem (CRT) termed the New CRT II. The new form of the CRT does not require the modulo M operation, where M is the residue number system range, but a certain number of multipliers is needed. Because in the FPGA environments the multipliers or the special DSP blocks are available, so they can be used in the converter realization. The main aim of the work is to examine experimentally the needed hardware amount and the influence of the multipliers on the maximum pipelining frequency. In Part I the derivation of the conversion algorithm is described. In Part II the hardware implementation of the converter in the FPGA technology is shown.