Behavioural synthesis utiization for hardare implementation of an RSA cryptosystem

This paper deals with a hardware implementation of an RSA cryptosystem. A behavioural and RT-level model of the RSA cryptosystem was created. The authors focus particularly on the behavioural model. The behavioural model is fully parameterized and was synthesized for keys of two lengths and several clock speeds. The paper encloses sunthesis results regarding area and performance in meaning of time needed to pass the whole computation cycle. Basing on them a comparison is carried out for behavioural and RT-level implementation.