A flexible, high performance hardware implementation of the simplified histogram of oriented gradients descriptor

In this paper, a high performance, configurable, compact hardware architecture for computing the histogram of oriented gradients (HoG) descriptors is presented. The descriptor computation algorithm is simplified w.r.t. to the original solution, enabling hardware resource cost reduction with only a small accuracy penalty. The proposed architecture can be accommodated to different block sizes and different block grid configurations, enabling its use in a wide range of object detection and recognition tasks with varying region of interest sizes. The resulting architecture is systolic and massively parallel, enabling high throughput processing.

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Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).