Efficient Implementation of Fractional Sampling Rate Conversion (SRC) on FPGA

Field Programmable Gate Arrays (FPGAs) include versatile features, which make them useful for use in Digital Signal Processing (DSP)-based systems that require high levels of performance. This paper introduces hardware implementation of decimator (M), Interpolator (L), and Sample Rate Conversion (SRC) by factor L/M, using different structure realizations (direct, efficient, and polyphase). Initially, a digital low-pass Finite Impulse Response (FIR) filter is designed using the Remez algorithm for filter coefficient calculation and realized with a decimator (M=2), an Interpolator (I=5), and SRC (5/2). These design structures are implemented using Xilinx Simulink blocks on the Artix 7 (XC7A-1csg324) FPGA development board. In the decimator, the polyphase structure represents the best design in terms of resource utilization, such as registers, Look Up Table (LUT), flip-flops, total real-time, memory usage, and multiplexers, while the direct structure consumes more resources. The same results are in the Interpolator. For SRC, it can be noted that the efficient design with linear phase is better in terms of device utilizations, while the direct structure is best in the number of unique control sets and number of multiplexers.