Implementation of fast uniform random number generator on FPGA

The article presents approach to implementation of random number generator on FPGA unit. The objective was to select a generator with good properties (correlation values and matching of probability density function were taken into account). Design focused on logical elements so that the pseudo-random number generation time depend only on the electrical properties of the system. The results are positive, because the longest time determining the pseudorandom number was 16.7ns for the “slow model” of the FPGA and 7.3ns for “fast model”, while one clock cycle lasts 20ns.