FPGA Implementation of Turbo Decoders Using the BCJR Algorithm

The most challenging design issue for turbo codes, which is a successful channel coding method to approach the channel capacity limit, is the design of the iterative decoders which perform calculations for all possible states of the encoders. BCJR (MAP) algorithm, which is used for turbo decoders, embodies complex mathematical operations such as division, exponential and logarithm calculations. Therefore, BCJR algorithm was avoided and the sub-optimal derivatives of this algorithm such as Log-MAP and Max-Log-MAP were preferred for turbo decoder implementations. BCJR algorithm was reformulated and wrapped into a suitable structure for FPGA implementations in previous works. Previously reformulated BCJR algorithm was implemented and discussed in this paper for several design issues. Implemented system is verified through simulations. It is observed that the BER performance of the proposed algorithm is better than the Log-MAP algorithm as expected. Despite its superior BER performance, the proposed BCJR turbo decoder has a clear throughput disadvantage. For this reason the decoder has been duplicated. This is done by simply inserting another BCJR turbo decoder on the same FPGA platform, enabling two operating decoders at the same time interval. This simple yet effective modification yields almost doubled throughput results compared to the single BCJR decoder.

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W artykule przedstawiono koncepcję budowy turbo dekodera opartego na algorytmie BCJR, zaimplementowanego w układzie FPGA. W celu ułatwienia programowania, zastosowano specjalną strukturę opracowanej metody. Ze względu na ograniczenia przepustowości dekodera, zastosowano dwa takie algorytmy, działające na platformie sterującej równolegle. Pozwoliło to na prawie dwukrotne zwiększenie przepustowości.