Dynamic comparator design in 28 nm CMOS

The paper presents a dynamic comparator design in 28 nm CMOS process. The proposed comparator is a main block of an asynchronous analog-to-digital converter used in a multichannel integrated circuit dedicated for X-ray imaging systems. We provide comparator’s main parameters analysis, i.e. voltage offsets, power consumption, response delay, and input-referred noise in terms of its dimensioning and biasing. The final circuit occupies 5×5 μm2 of area, consumes 17.1 fJ for single comparison with 250 ps of propagation delay, and allows to work with 4 GHz clock signal.

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Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2020).