Parallel uniform random number generator in FPGA

The article presents approach to implementation of random number generator in FPGA unit. The objective was to select a generator with good properties (correlation values and fidelity of probability density function were taken into account). During the design focused on logical elements so that the pseudo-random number generation time depend only on the electrical properties of the system. The results are positive, because the longest time determining the pseudorandom number was 16.7ns for the “slow model” of the FPGA and 7.3ns for “fast model”, while one clock cycle lasts 20ns. Additionally the parallel random number generator has been proposed, composed of 10 simple generator modules. After modules connecting, maximum time for generation of 10 random numbers was equal 41.0ns for the “slow model” and 16.6ns for the “fast model”.