A low-jitter, full-differential PLL in 0.18μm CMOS technology

This paper presents a Phase Locked Loop (PLL) which works with minimum jitter in the operation frequency range of 600MHZ to 900MHZ. Utilizing a full differential architecture that consists of several blocks of differential VCO, a differential PFD and a differential CPL leads to limiting the RMS jitter to 4.06ps, with 50mV power supply noise in the frequency range of 750MHz. Simulation results using 0.18μm CMOS TSMC standard technology demonstrate the power-consumption of 4.6mW at the supply voltage of 1.8V.