Systolic Array Design Using New Simulator

This paper presents a method of mapping computational algorithms onto special VLSI systems - Systolic Arrays. This method is a fundamental tool for description of the algorithm for parallel and pipeline processing. This paper shows designing process of Systolic Arrays at the functional level (instructions), and at the structural level (processing elements), generated with the application of a special Systolic Array Simulator, which has been designed for the purpose of this research. Systolic Arrays are characterized by proper adaptation of time-space algorithms to the corresponding system architecture. Computational problem has been presented in a graphical form, as a Dependence Graph, and subsequently, as a Signal Flow Graph. After introducing delays to the data sequence in a Signal Flow Graph, the particular designs of Systolic Array architectures have been obtained. The article shows, as well, an application of the Systolic Array Simulator to the problem of multiplying a matrix by a matrix. In similar way, Systolic Array can be created for performing Discrete Transforms, computing convolutions, digital filters or neural networks.