Design a High-Performance Memory Controller for a Multimedia SOC

Continuously growing functionalities of modern consuming electronics make the major multimedia SOC (system-on-a-chip) chip more complex. Moreover, the integrated multimedia processors and the required memory bandwidth are increasing. Therein how to improve the performance of the memory controller will become a major challenge of designing a modern multimedia SOC. According to our previous study of multimedia SOC, to achieving the bandwidth requirements are not only by improving memory throughput but also by dynamically adjusting the bandwidth usage of multimedia processors. Therefore we develop novel memory subsystem, called Smart Memory Controller (SMC), which integrates a novel scheduling/arbitration mechanism, a unified access buffer, multi-level memory access classification/scheduling, and several corresponding hardware modules, to provide a sufficient memory bandwidth for the multimedia processors with high bandwidth requirements. The proposed SMC architecture has been implemented by SystemC/Bluespec/Verilog HDL. The experimental results from whole SMC system illustrates that SMC will arrange enough bandwidth for the channels that have bursting transferring requirement. The fabrication results of SMC are also provided.

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W artykule zaproponowano nowy system pamięci nazwany SMC (smart memory controller) przeznaczony do multimedialnych elementów typu SOC (system on a chip). System integruje mechanizm planowania i arbitrażu (scheduling/arbitration), bufor dostępu, wielopoziomowy dostęp do pamięci i wiele innych modułów.