3D ICs layout hypergraph representation

The paper presents a knowledge intensive graphical 3D ICs layout representation in the form of hierarchical layout hypergraphs that enable to demonstrate all possible relations among chip components, especially spatial relations in 3D spaces. The introduction of the hierarchy enables to gather and retrieve information on different levels of details. The proposed graphical knowledge description is also suitable for the grid like neighborhood representation that may be used to divide the circuit into layers.